1. Field of the Invention
The present invention relates to a logic circuit such as a NAND circuit or an NOR circuit. Such a logic circuit is often used in address decoders, a bit line control clock generator circuit, etc of a memory device.
2. Description of the Prior Art
A prior art logic circuit such as a NAND circuit or a NOR circuit comprises a load, a single driver circuit driven by the potentials at two or more input terminals, and an output terminal connected between the load and the driver circuit. The driver circuit has a plurality of gates which are driven by the potentials at the input terminals.
In the above-mentioned prior art, however, the presence or absence of charges at an intermediate node of the gates generates a fluctuation in operation speed. In this case, the operation speed is dependent upon the condition of input signals. As a result, the overall operation speed is substantially reduced.